JPH0337220B2 - - Google Patents

Info

Publication number
JPH0337220B2
JPH0337220B2 JP59185983A JP18598384A JPH0337220B2 JP H0337220 B2 JPH0337220 B2 JP H0337220B2 JP 59185983 A JP59185983 A JP 59185983A JP 18598384 A JP18598384 A JP 18598384A JP H0337220 B2 JPH0337220 B2 JP H0337220B2
Authority
JP
Japan
Prior art keywords
input
interrupt
cpu
output
interrupt information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP59185983A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6182260A (ja
Inventor
Tadashi Hanada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59185983A priority Critical patent/JPS6182260A/ja
Publication of JPS6182260A publication Critical patent/JPS6182260A/ja
Publication of JPH0337220B2 publication Critical patent/JPH0337220B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP59185983A 1984-09-05 1984-09-05 入出力割込み制御方式 Granted JPS6182260A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59185983A JPS6182260A (ja) 1984-09-05 1984-09-05 入出力割込み制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59185983A JPS6182260A (ja) 1984-09-05 1984-09-05 入出力割込み制御方式

Publications (2)

Publication Number Publication Date
JPS6182260A JPS6182260A (ja) 1986-04-25
JPH0337220B2 true JPH0337220B2 (en]) 1991-06-04

Family

ID=16180304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59185983A Granted JPS6182260A (ja) 1984-09-05 1984-09-05 入出力割込み制御方式

Country Status (1)

Country Link
JP (1) JPS6182260A (en])

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7849247B2 (en) * 2008-10-14 2010-12-07 Freescale Semiconductor, Inc. Interrupt controller for accelerated interrupt handling in a data processing system and method thereof

Also Published As

Publication number Publication date
JPS6182260A (ja) 1986-04-25

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